CacheSim
Introduction
CacheSim is a trace-driven cache simulator that implements the Write Back Write Allocate policy. It is generic and can be instantiated at any level in the memory hierarchy - L1, L2, or L3. It is also flexible and can be configured to support any cache size, block size, or associativity. Furthermore, CacheSim can be augmented with a stream-buffer prefetch unit whose size (# of stream buffers) and degree (# of blocks prefetched) is specified at the start of simulation.
CacheSim was built to compare the performance, area, and energy of different memory hierarchy configurations using a subset of the SPEC 2006 and SPEC 2007 benchmark suites.
🤖 Working
- A cache receives a R/W request from a level above it in the memory hierarchy (either the CPU or another cache).
- A cache interacts with the level below it only when it suffers from a R/W miss. It issues a R request to the next level and has to allocate the requested block.
- A block is allocated in the cache in two steps:
- Making space for the requested block X - If there is at least one invalid block in the set, then there is already space for the requested block X and no further action is required. If not, then the LRU block is evicted by issuing a write to the next level.
- Bringing in the requested block X - Issue a R request to the next level in memory hierarchy and place X in the set.
- The LRU counters associated with the blocks in a set are updated on every access. Blocks are also marked dirty when written to and invalid when evicted.
Introducing a stream buffer prefetch unit adds another layer of complexity to CacheSim. The prefetch unit can support N stream buffers each of which has a degree M. Each buffer has a valid bit that indicates the validity of the buffer as a whole. A valid bit of 0 implies that the buffer is empty and 1 implies that the buffer is full and contains M consecutive memory blocks. A R/W request for a block X has to now search both the cache and the stream buffer(s). As such, there are four possible scenarios.
- Create a new prefetch stream: requested block misses in the cache and stream buffer
- Benefit from and continue a prefetch stream: Requested block misses in the cache but hits in the stream buffer